Uniform tiling with electrical resistors

Identification of Resistors in Electrical Networks

The purpose of this work is to identify the internal structure of the electrical networks with data obtained from only a part of network or the boundary of network. To be precise, it is discussed whether we can identify resistors or electrical conductivities of each link inside networks by the measurement of voltage on the boundary which is induced by a prescribed current on the boundary. As a ...

Precise Tiling for Uniform Loop Nests

Optimal Tiling of Two-Dimensional Uniform Recurrences

Iteration space tiling is a common strategy used by parallelizing compilers and in performance tuning of parallel codes. We address the problem of determining the tile size that minimizes the total execution time of such a program. We restrict our attention to uniform dependency computations which have a parallelogram shaped two dimensional iteration space, and the target architecture is a line...

Communication-Minimal Tiling of Uniform Dependence Loops

Tiling is a loop transformation that a compiler uses to create automatically blocked algorithms in order to improve the benefits of the memory hierarchy and reduce the communication overhead between processors. Motivated by existing results, this paper presents a conceptually simple approach to finding tilings with a minimal amount of communication between tiles. The development of almost all r...

Minimum degree condition for C4-tiling in 3-uniform hypergraphs

We show that there is n0 such that if H is a 3-uniform hypergraph on n ∈ 4Z, n ≥ n0, vertices such that δ1(H) ≥ ( n−1 2 ) − ( 3n/4 2 ) + 3n 8 + 1 2 , then H can be tiled with copies of C4, the unique 3-uniform hypergraph on four vertices with two edges. The degree condition is tight when 8|n.